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this is information on a product in full production. march 2012 doc id 14174 rev 10 1/25 25 vni4140k quad high-side smart power solid-state relay datasheet ? production data features output current: 0.7 a per channel shorted load protections junction overtemperature protection case overtemperature protection for thermal independence of the channels thermal case shutdown restart not simultaneous for the various channels protection against loss of ground current limitation undervoltage shutdown open drain diagnostic outputs 3.3 v cmos/ttl compatible inputs fast demagnetization of inductive loads conforms to iec 61131-2 esd according to iec 61000-4-2 up to +/- 25 kv figure 1. block diagram description the vni4140k is a monolithic device made using stmicroelectronics vipower technology, intended for driving four independent resistive or inductive loads with one side connected to ground. active current limitation avoids dropping the system power supply in case of shorted load. built-in thermal shutdown protects the chip from overtemperature and short-circuit. in overload condition, channel turns off and back on automatically so as to maintain junction temperature between t tsd and t r . if this condition makes case temperature reach t csd , overloaded channel is turned off and will restartonly when case temperature has decreased down to t cr . in case of more than one channel in overload, re-start of the overloaded channels will not be simultaneous, in order to avoid high peak current from the supply. non overloaded channels continue to operate normally. the open drain diagnostics outputs indicates overtemperature conditions. type v demag (1) 1. per channel. r ds(on) (1) i out (1) v cc vni4140k v cc -41 v 0.08 ? 0.7 a 41 v powersso-24 www.st.com
contents vni1440k 2/25 doc id 14174 rev 10 contents 1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 package and pc board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 vni4140k thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
vni1440k pin connection doc id 14174 rev 10 3/25 1 pin connection figure 2. pin connection (top view) table 1. pin description pin name description tab tab exposed tab internally connected to vcc 1 vcc supply voltage 2 in1 channel 1 input 3.3 v cmos/ttl compatible 3 stat1 channel 1 status in open drain configuration 4 in2 channel 2 input 3.3 v cmos/ttl compatible 5 sta2 channel 2 status in open drain configuration 6 gnd device ground connection 7 stat3 channel 3 status in open drain configuration 8 in3 channel 3 input 3.3 v cmos/ttl compatible 9 stat4 channel 4 status in open drain configuration 10 in4 channel 4 input 3.3 v cmos/ttl compatible 11 nc 12 nc 13 out4 channel 4 power stage output, internally protected 14 out4 channel 4 power stage output, internally protected 15 out4 channel 4 power stage output, internally protected 16 out3 channel 3 power stage output, internally protected 17 out3 channel 3 power stage output, internally protected out1 out1 out1 out2 out2 out2 v cc in1 stat1 in2 stat2 gnd out3 out3 out3 out4 out4 out4 stat3 in3 stat4 nc nc in4
pin connection vni1440k 4/25 doc id 14174 rev 10 pin name description 18 out3 channel 3 power stage output, internally protected 19 out2 channel 2 power stage output, internally protected 20 out2 channel 2 power stage output, internally protected 21 out2 channel 2 power stage output, internally protected 22 out1 channel 1 power stage output, internally protected 23 out1 channel 1 power stage output, internally protected 24 out1 channel 1 power stage output, internally protected table 1. pin description (continued)
vni1440k maximum ratings doc id 14174 rev 10 5/25 2 maximum ratings 2.1 thermal data table 2. absolute maximum rating symbol parameter value unit v cc power supply voltage 41 v -v cc reverse supply voltage -0.3 v i gnd dc ground reverse current -250 ma i out output current (continuos) internally limited a i r reverse output current (per channel) -5 a i in input current (per channel) 10 ma v in input voltage +v cc v v stat status pin voltage +v cc v i stat status pin current 10 ma v esd electrostatic discharge (r = 1.5 k ? ; c = 100 pf) 2000 v e as single pulse avalanche energy per channel not simultaneously 300 mj p tot power dissipation at t c = 25 c internally limited w t j junction operating temperature internally limited c t stg storage temperature -55 to 150 c table 3. thermal data symbol parameter value unit r th(jc) thermal resistance junction-case (1) 1. per channel max 2 c/w r th(ja) thermal resistance junction-ambient max see figure 11 c/w
electrical characteristics vni1440k 6/25 doc id 14174 rev 10 3 electrical characteristics 10.5 v < v cc < 36 v; -25 c < t j < 125 c; unless otherwise specified v cc = 24 v; -25 c < t j < 125 c, r l = 48 ? , input rise time < 0.1 s table 4. power section symbol parameter test condition min typ max unit vcc supply voltage 10.5 36 v r ds(on) on-state resistance i out = 0.5 a at t j = 25 c i out = 0.5 a 0.080 0.140 ? ? v clamp i s = 20 ma 41 45 52 v i s supply current all channel in off state on state with v in = 5 v (t j = 125 c) 250 2.4 4 a ma i lgnd output current at turn- off v cc = v stat = v in = v gnd = 24 v, v out = 0 v 1ma v out(off) off state output voltage v in = 0 v and i out = 0 a 1 v i out(off) off state output current v in = v out = 0 v 0 5 a f cp charge pump frequency channel in on state (1) 1. to cover en55022 class a and class b normative. 1450 khz table 5. switching symbol parameter min typ max unit t d (on) turn on delay - 20 - s t r rise time - 10 - s t d (off) turn off - 30 - s t f fall time - 8 - s dv/dt (on) turn on voltage slope - 3 - v/s dv/dt (off) turn off voltage slope - 4 - v/s
vni1440k electrical characteristics doc id 14174 rev 10 7/25 table 6. logical input symbol parameter test condition min typ max unit v il input low level voltage 0.8 v v ih input high level voltage 2.20 v v i(hyst) input hysteresis voltage 0.15 v i in input current v in = 15 v 10 ? v in = 36 v 210 table 7. protection and diagnostic symbol parameter test condition min typ max unit v stat status voltage output low i stat = 1.6 ma 0.6 v v usd undervoltage protection 710.5v v usdhys undervoltage hysteresis 0.4 0.5 v i lim dc short-circuit current v cc = 24 v; r load < 10 m ? 0.7 1 1.7 a i peak maximum dc output current dynamic load 1.3 a hyst tracking limits 0.2 a i lstat status leakage current v cc = v stat = 36 v 30 ? t tsd junction shutdown temperature 150 170 190 c t r junction reset temperature 135 c t hist junction thermal hysteresis 715 c t csd case shutdown temperature 125 130 135 c t cr case reset temperature 110 c t chyst case thermal hysteresis 715 c v demag output voltage at turn-off i out = 0.5 a; l load >= 1 mh v cc - 41 v cc - 45 v cc - 52 v
electrical characteristics vni1440k 8/25 doc id 14174 rev 10 figure 3. current and voltage conventions
vni1440k truth table doc id 14174 rev 10 9/25 4 truth table 5 typical application circuit figure 4. typical application circuit table 8. truth table condition inputn outputn statusn normal operation l h l h h h overtemperature l h l l h l undervoltage l h l l x x shorted load (current limitation) l h l x h h
typical application circuit vni1440k 10/25 doc id 14174 rev 10 figure 5. thermal behavior no tj ( i ) > tt s d vi n ( i ) = h out(i) off stat(i) on (l) tc > tc s d no yes no yes tc > tc r yes no tj(i) > tjr yes stat(i) off (h) out(i) on 1) 4) 2) 3)
vni1440k switching waveforms doc id 14174 rev 10 11/25 6 switching waveforms figure 6. switching waveforms
pin functions vni1440k 12/25 doc id 14174 rev 10 7 pin functions figure 7. input circuit figure 8. status circuit
vni1440k pin functions doc id 14174 rev 10 13/25 figure 9. charge pump switching frequency (typical) vs temperature freq_cp 800 1000 1200 1400 1600 1800 2000 -50 0 50 100 150 200 temperature("c) cp_frequency (khz) freq_cp
package and pc board thermal data vni1440k 14/25 doc id 14174 rev 10 8 package and pc board thermal data 8.1 vni4140k thermal data figure 10. vni4140k pc board note: layout condition of rth and zth measurements (pcb: double layer, thermal vias, fr4 area = 77 mm x 86 mm, pcb thickness=1.6 mm, cu thickness = 70 mm (front and back side), copper areas: from minimum pad lay-out to 8 cm 2 ). figure 11. r thja vs pcb copper area in open box free air condition (one channel on)
vni1440k package and pc board thermal data doc id 14174 rev 10 15/25 figure 12. vni4140k thermal impeda nce junction ambient single pulse (one channel on)
reverse polarity protection vni1440k 16/25 doc id 14174 rev 10 9 reverse polarity protection this schematic can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. r gnd = (-v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. power dissipation in r gnd (when v cc < 0: during reverse polarity situations) is: pd = (-v cc ) 2 /r gnd note: in normal condition (no reverse polarity) due to the diode there will be a voltage drop between gnd of the device and gnd of the system. figure 13. reverse polarity protection status i input i gnd output i + vcc r gnd load diode status i input i gnd output i + vcc r gnd load diode
vni1440k package mechanical data doc id 14174 rev 10 17/25 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data vni1440k 18/25 doc id 14174 rev 10 figure 14. powersso-24 package dimensions table 9. powersso-24 mechanical data symbol mm min. typ. max. a 2.15 2.47 a2 2.15 2.40 a1 0 0.075 b 0.33 0.51 c 0.23 0.32 d 10.10 10.50 e 7.4 7.6 e 0.8 e3 8.8 g 0.1 g1 0.06 h 10.1 10.5 h 0.4 l 0.55 0.85 n 10deg x 4.1 4.7 y 6.5 7.1
vni1440k package mechanical data doc id 14174 rev 10 19/25 figure 15. powersso-24 tube shipment (no suffix) note: all dimensions are in mm. table 10. powersso-24 tube shipment base quantity 49 bulk quantity 1225 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6
package mechanical data vni1440k 20/25 doc id 14174 rev 10 figure 16. powersso-24 reel shipment (suffix ?tr?) table 11. powersso-24 reel dimensions base quantity 1000 bulk quantity 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (2 0) 24.4 n (min) 100 t (max) 30.4
vni1440k package mechanical data doc id 14174 rev 10 21/25 figure 17. powersso-24? tape dimensions note: according to electronic industries association (eia) standard 481 rev. a, feb 1986 table 12. powersso-24? tape dimensions tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.05) 1.55 hole diameter d1 (min) 1.5 hole position f ( 0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 ( 0.1) 2
package mechanical data vni1440k 22/25 doc id 14174 rev 10 figure 18. vn14140k suggested footprint note: stmicroelectronics is not responsible for any pcb related issues. the footprint shown in the above figure is a suggestion which might not be in line to the customer pcb supplier design rules. all dimensions are in mm. 3older-ask/pening 2 n
vni1440k order codes doc id 14174 rev 10 23/25 11 order codes table 13. order codes order codes package packaging vni4140k powersso-24 tube VNI4140KTR powersso-24 tape and reel
revision history vni1440k 24/25 doc id 14174 rev 10 12 revision history table 14. document revision history date revision changes 16-nov-2007 1 initial release 26-nov-2007 2 updated electrical parameters values 08-jul-2008 3 inserted: figure 4 on page 9 and section 9: reverse polarity protection on page 16 08-apr-2008 4 added i lgnd parameter in table 4 on page 6 27-aug-2009 5 updated section 9: reverse polarity protection 09-dec-2009 6 added section 10: conformity to iec 61000-4-2 esd immunity test 15-apr-2010 7 updated table 5 on page 6 06-feb-2012 8 inserted feature: conformity to iec 61000-4-2 esd immunity test in cover page. removed chapter: conformity to iec 61000-4-2 esd immunity test. 05-mar-2012 9 suggested footprint inserted. in table 4. parameter i lgnd has been added. 19-mar-2012 10 minor text changes.
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